In a forwarded clock system such as for an interconnect in a computer system, incoming data at a receiver is sampled by a transmitted clock. Upon entering the receiving agent, the clock is provided to a delay lock loop (DLL), which can generate multiple clock phases. To ensure that the data is sampled in the middle of the data eye, with maximum setup and hold time to allow for as much timing margin as possible, a phase interpolator (PI) produces a refined clock edge which is then used to sample the data. The PI settings are programmed by means of an interpolator filter and control block. This block processes the sampled data at all PI positions and adjusts the PI setting to produce a sampling clock that is phase aligned with the incoming data. This is done during initial training and periodic re-training periods. The periodic re-training accounts for drift of the skew between the input data and the forwarded clock input. However, such training can be cumbersome and require substantial amounts of time, as uncertainty in PI initialization can occur, as with a small effective eye width, the sampling eye generated by the PI can be outside the data eye.